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Proxelera is India's premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We also offer you unparalleled quality of service in productization of your chip through reference system design and system software development.
Position: PD Lead (Cadence Innovus )
Experience: 6-9 Yrs
Location: Hyderabad
Job Description:
Basic Job Deliverable:
Qualification:
Job ID: 147217683
Skills:
Python, Routing, Perl, Tcl, physical design methodologies, floor-planning, CTS, Synopsys Fusion Compiler, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, floor plan synthesis, Synthesis, Apache Redhawk, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Cadence PrimeTime, Placement
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, DRC, Timing Closure, Cadence PrimeTime, Placement
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, CTS, floor-planning, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime
Skills:
redhawk , Physical Verification, PNR and signoff tools, Physical design implementation, Cadence Innovus, IR EM mitigation, STA constraints, primetime, Synopsys ICC2, Tempus, Power grid and PDN methodology, Voltus, Floorplanning and partitioning strategies
Skills:
Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff
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