Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

performance verification of ASICs, assertion-based verification, Uvm, formal tools, ASIC standard interfaces, systemverilog, Design Verification, memory system architecture, verification components

Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB

DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim

simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

Computer Architecture, Verilog, Uvm, systemverilog, coverage-driven verification, advanced stimulus generation

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB

Ovm, Pcie, CHI, Uvm, cache coherency concepts, CXL, systemverilog, Ace, Axi, interconnect and bus protocols, AMBA

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB