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Role : Design Verification
Exp : 7-16 Years
Location: Bangalore ;
Job Description:
Primary Skills
Secondary Skills
Job ID: 151223517
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification
Skills:
Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage
Skills:
analog circuits , Fpga, Logic Design, Verilog, Micro-architecture, Synthesis, Uvm, Timing Constraints, Regression frameworks, Power product design, System-Verilog, Functional Verification, RTL Coding, Sta, Synthesis scripts, ATPG generation, Scan Insertion, formal verification, ABV, Timing Analysis, Digital Verification