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Role : Design Verification
Exp : 7-16 Years
Location: Bangalore ;
Job Description:
Primary Skills
Secondary Skills
Job ID: 151223517
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts
Skills:
System Verilog, regression systems, industry-standard simulators, verification components, revision control systems
Skills:
Ovm, DDR, Pcie, Perl, Verilog, Ethernet, Python, System Verilog, Tcl, UCIE, Uvm, CXL
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim