Ant, Mentor Calibre, Memory analog layout design, floorplanning, high speed GHz circuit design, LVS, Latch-up, CMOS process geometries, signal and clock shielding, EMIR, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, DRC, signal flow planning, isolation techniques, Cadence Virtuoso, Reliability

DRC, LVS, semiconductor fundamentals, Parasitic Extraction, Cadence Virtuoso, ERC, precision analog layouts, analog layout design, CMOS technology

Python, EMIR, Skill, DRC, chip assembly techniques, AMS Layout Verification flows, LVS, Cadence Virtuoso

Python, Cadence Virtuoso, EMIR, chip assembly techniques, LVS, AMS Layout Verification flows, DRC, Skill

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

Mentor Graphic Caliber, Cadence VLE, LVS, DRC, Antenna quality check

Parasitic effects, LVS DRC PEX EMIR verification flows, xACT, Reference circuits, Calibre DRC, Bandgap Oscillators, StarRC

Ant, Mentor Calibre, CMP effects, floorplanning, high speed GHz circuit design, LVS, 7nm and below CMOS process geometries, Latch-up, signal and clock shielding, EMIR, process non-idealities, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, well proximity effect, DRC, signal flow planning, isolation techniques, STI stress, Cadence Virtuoso, Reliability

Ant, Latch-up, 7nm and below CMOS process geometries, Reliability, high speed GHz circuit design, LVS, process non-idealities, floorplanning, layout design for mixed analog digital ICs, Mentor Calibre, EMIR, Esd, signal flow planning, Cadence Virtuoso, ERC, DRC, isolation techniques, high performance data converters, signal and clock shielding