Sta, RTL2GDS, physical design EDA tools, Cadence, Synopsys, Synopsis Primetime

STA Engineer, constraint development

Static Timing Analysis, Sta, Digital Design

DFT modes in STA timing closure, RTL-to-GDSII implementation, Constraint creation and maintenance, PPA optimization, Timing closure fundamentals

EDA tool, Sta, DFT modes requirements, SDC constraints, TCL/scripting, SDC construct

System Verilog, Perl scripting, Tcl Scripting, Sta, SDC, RTL, Application Engineering

Timing constraint development, RTL to Netlist Logical equivalence check, Digital Synthesis, Timing Analysis, STA flow setup, Physical Verification, EM IR flows, DFT insertion, Timing Noise DRC, Signoff checks