Packaging, Layout Design, digital layout, SI PI, Circuit Design, mixed-signal circuits

power management, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, DRC, Electrical check, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs

static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, SystemVerilog RTL design, Lint CDC formal verification, DFT including scan testability, Logic Synthesis