Principal Design Engineer
Principal Design Engineer
CADENCEThis job is no longer accepting applications
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
The Principal AMS Design Engineer will be a key contributor to the HBM PHY team, responsible for the design and development of high-speed analog and mixed-signal circuits for next-generation HBM PHY products. This role includes detailed circuit design based on system and micro-architecture requirements, leadership in analog and layout design reviews, and close collaboration with cross‑functional teams including digital, layout, packaging, and SI/PI. The engineer will take ownership of project execution across development phases and play a critical role in driving new micro‑architecture innovations to meet aggressive performance, power, and area targets for advanced HBM PHY designs.
We're doing work that matters. Help us solve what others can't.
Job Description
The Principal AMS Design Engineer will be a key contributor to the HBM PHY team, responsible for the design and development of high-speed analog and mixed-signal circuits for next-generation HBM PHY products. This role includes detailed circuit design based on system and micro-architecture requirements, leadership in analog and layout design reviews, and close collaboration with cross‑functional teams including digital, layout, packaging, and SI/PI. The engineer will take ownership of project execution across development phases and play a critical role in driving new micro‑architecture innovations to meet aggressive performance, power, and area targets for advanced HBM PHY designs.
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
About Company
Skills:
Packaging, Layout Design, digital layout, SI PI, Circuit Design, mixed-signal circuits
Skills:
power management, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, DRC, Electrical check, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs
Skills:
static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, SystemVerilog RTL design, Lint CDC formal verification, DFT including scan testability, Logic Synthesis