C, MATLAB, Perl, Python, RF ADE, systemverilog, Parasitic Extraction, Spectre, CMOS, SERDES, Cadence Virtuoso, Mixed-Signal Verification, Verilog-A

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

System Verilog, Environment Development, Uvm, Design Verification, Functional Verification, Test Plan Generation

power optimization , Verilog, static timing analysis, Uvm, Synopsys, SV-based testbenches, Timing Analysis, Mentor Graphics, digital design flow, EDA Tools, coverage-driven verification, systemverilog, Rtl Design, Cadence, VHDL, Simulation