Test Methodology, DFT Architecture, Scan Insertion, Fault Simulation, DFT Tools, Debugging Skills, Rtl Design, Synthesis Tools, Timing Analysis, Tape-out Process

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, ATPG coverage analysis, equivalence check, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes, DFT DRC rules