C, Tcl, Python, Perl, PrimeSim, LVS, CMOS design, Spectre, ADE, high-speed analog design, Custom Compiler, post-layout extraction, Cadence Virtuoso, DRC, Hspice, Circuit Simulation

bandgap references , Comparators, Statistics, MOS Diodes, Transistor layout fabrication process, Analog Circuit Design, Monte Carlo analysis, Level Shifter, Schmitt Trigger, Statistical Distributions, Schematic generation, LDMOS, ESD protection circuits for CMOS IC, Power FETs, Amplifiers, Current Mirrors

bandgap references , Usb, Pi, Ddr3, Dll, Sata, Pcie, DFE, Bias generator, High speed Memory interfaces, Clktree, SerDes Interfaces, MIPI, Charge pump, HDMI, Analog mixed signal CMOS circuits, HBM2E SoC analog sub-block design, DDR5, Rx CDR, GDDR5, OPamps, LDO, LPDDR3, Tx PLL, Comparators

matching , rc extraction , shielding , bandgap references , Perl, Tcl, ADC, latch-up strategies, Skill, high-speed analog custom layout, LVS, Power Planning, Dfm, Pll, clock routing, SERDES, Esd, EDA Tools, ERC, EMIR analysis, DRC, Cadence Virtuoso, LDOs

ESD concepts, JEDEC DDR interface requirements, ASIC design flow, DDR Timing, analog mixed signal design methodologies, SDRAM functionality, CMOS Circuit Design, layout methodologies, ODT

CMOS Circuit Design, Deep submicron process technology, Analog/mixed-signal circuitry basics, DDR/HBM memory interface design, ASIC design flow, JEDEC standards for DDR interfaces

bandgap references , regulators , Data-path analog blocks, Interface Circuits, PLL clock-generation, Mixed-signal circuit design, Layout collaboration, Custom analog design, Charge Pumps, Analog Design, Transistor-level design, Parasitic-aware optimization, Loop Filters, Bias circuits, Simulation and optimization

lean engineering , Sustenance Engineering, Design controls process, Project management, CAD packages, Statistics and verification methods, medical device product development, Lean product development methodologies