test coverage , Jtag, gate-level, stuck-at, memory test strategies, full scan compression, BSCAN, DFT simulation, debug RTL, MBIST, Cadence, transition at-speed, SoC test architecture, iJTAG, test quality metrics, ATPG, industry DFT tools, Siemens, Synopsys, Scan architectures, hierarchical DFT

DFT verification, DFT Insertion, ATE Pattern Development, DFT concepts, RTL lint tool, BSCAN, MBIST, ATPG Coverage Analysis, equivalence check, ATE support, Scan, spyglass, IJTAG, Netlist level Insertion