Job Title: Lead DFT Engineer / DFT Manager
Experience: 10–18 Years
Location: Bangalore
Role Summary:
We are looking for a senior DFT professional to lead DFT strategy, execution, and team delivery for complex SoCs/IPs. This role requires strong hands-on DFT expertise along with team leadership, technical ownership, and cross-functional coordination.
Key Responsibilities:
- Lead end-to-end DFT architecture, implementation, and signoff for SoC/IP programs
- Define and own DFT strategy: Scan architectures, JTAG / iJTAG, BSCAN, ATPG, MBIST
- Review and approve DFT plans, test architectures, and coverage targets
- Drive ATPG, MBIST, and DFT simulation flows and signoff quality
- Lead silicon bring-up, debug, and yield improvement from a DFT perspective
- Manage and mentor a team of DFT engineers (task allocation, reviews, technical guidance)
- Conduct design and DFT reviews with stakeholders (Design, PD, Validation, Product)
- Drive schedule, risk management, and delivery commitments for DFT milestones
- Establish and improve DFT methodologies, best practices, and automation
- Interface with customers/management on DFT status, issues, and plans
Required Technical Skills:
- Strong hands-on experience in:
- JTAG / iJTAG, BSCAN
- Scan architectures (full scan, compression, hierarchical DFT)
- ATPG (stuck-at, transition, at-speed)
- MBIST and memory test strategies
- DFT simulation and debug (RTL and gate-level)
- Solid understanding of SoC test architecture, test coverage, and test quality metrics
- Experience with industry DFT tools (Synopsys / Cadence / Siemens or equivalent)
Leadership / Management Requirements:
- Proven experience as a Team Lead / Technical Lead / DFT Manager
- Experience in:
- Leading and mentoring engineers
- Technical reviews and signoff ownership
- Planning and tracking deliverables across multiple projects
- Stakeholder management and cross-team coordination
- Ability to drive technical decisions and resolve complex DFT issues
Good to Have:
- Experience with low-power DFT, IJTAG networks, advanced test compression
- Experience handling multiple SoCs or large, complex chips
- Customer-facing or program leadership experience
Education:
- B.Tech / M.Tech in Electronics / VLSI or related field
