LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Digital Logic Design, Micro-architecture design, SOC integration, RTL quality checks, Rtl Design

APB, RTL quality checks, Subsystem IP integration, Subsystem IP design, SoC integration, Microarchitecture, Axi, Rtl Design

Perl, ASIC, Digital Design, Sta, Circuit timing, Rtl Design