Switches, Vcs, Shell, Perl, Pcie, Ethernet, Python, Tcl, RDMA, Verdi, Emulation, Xcelium, NICs, Networking architectures, SmartNICs, Palladium, Cadence, systemverilog, FPGA prototyping, formal verification, Packet processing, Zebu, Questa

Pcie, Ethernet, Emulation, RISC-V architecture, Simulation, AMBA protocols, UCIe, assertion-based verification, Uvm, coverage-driven verification, FPGA prototyping, systemverilog, constrained-random verification, formal verification, high-performance SoC architectures, SERDES, CXL, hardware software co-verification

Technical Leadership, GLS debugging, Processor Interconnect Fabric, Strategic Problem Solving, High and Low speed peripherals, Digital SOC design principles, systemverilog, AXI protocols, Advanced Debugging, Memory Security Boot, Verification Strategy and Architecture, Verification Methodology Innovation, AHB

Verilog, System Verilog, Ovm, Jedec standards, DFI protocol, Low Power Verification, Uvm, Gate Simulation, formal verification, Design Verification, Functional Verification Coverage

Usb, C, Pcie, Ethernet, I2c, Python, validation methodologies, Flash architecture, emulation environments, ARM processors, lab test equipment, SERDES, NVMe storage protocols, FPGA prototyping flows, DDR5, LPDDR, I3C

Usb, Spi, Silicon Validation, Pcie, Scripting, design automation tools, Design Verification, RTL, Dft, Physical Design, MCU design, DMA, software validation