simvision , Cadence Tools, SV UVM-based mixed-signal testbench development, Xcelium, VIVA, Behavioral modeling using SV-RNM Verilog-AMS, SoC-AMS testbench development, Virtuoso ADE, Assembler

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Verilog, Python, Synopsys, low power design techniques, performance modeling tools, bus architectures, Cadence Tools, accelerators, memory hierarchies, arithmetic units

Test Plan Creation, Verilog, AHB, Uvm, UPF, DV environments, BFM, constrained random verification techniques, APB bus protocols, systemverilog, cdc, VHDL, CPF, block functional models, formal verification methodologies, RDC, Execution

Verilog, DO-254, VHDL, systemverilog, simulation debugging, traceability validation methodologies, coverage-driven verification

Tcl, Python, Perl, Pcie, Vcs, DDR, Uvm, Questa, systemverilog, APB, Axi, Verdi