Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Perl, Ruby, System Verilog, Asic verification, Rtl Design, make, Uvm, formal verification, TestBench Development

Verilog, Matlab, Python, FPGA-based emulation, DSP concepts

Perl, Ruby, System Verilog, make, Uvm

Verilog, Python, Synopsys, Cadence Tools, performance modeling tools, low power design techniques, arithmetic units, accelerators, memory hierarchies, bus architectures

Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog