scoreboard , System Verilog, verification environment, verification closure, script development, interface agents, Uvm, testbench components

Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB

Unix, Makefile, Shell, Configuration Management, PERL, System Verilog, Python, Verification dashboarding tools, ARM CPU, PCI Express, Uvm, AMBA bus protocols, Ethernet bus protocols

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

Python, System Verilog, Uvm, Gate Simulation, Coverage Closure, Asic verification