arm architecture , PERL, Python, Tcl, cdc, RTL constraints, LINT, SoC level design integration, Digital Design, timing exceptions, CHI protocols, Axi, standard quality checks, writing UPF, Timing Constraints, design reuse, automation using scripting techniques, APB, RTL Coding, designing with multiple power domains

Verilog, Logic Design, on-chip memory controller, verification processes, design simulation, Design Architecture, Schematics, RTL

Verilog, Soc, Timing Closure, IP integration, Synthesis, linting, systemverilog, ASIC, Digital Design, gate-level simulations

Linux Environment, Perl, Version Control Systems, Verilog, System Verilog, Python, Tcl, SOC tools, DFT technologies, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Synopsys Design Compiler, Questa CDC, VCS simulation

Perl, ASIC, Digital Design, Sta, Circuit timing, Rtl Design