Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Rtl Design, RTL quality checks, Micro-architecture design, SOC integration

Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Python Scripting, RTL design in Verilog SystemVerilog, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, PrimeTime or equivalent tools, C embedded experience, Circuit timing STA

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, FPGA design flow, Timing Closure, 5G LTE, Altera Agilex

conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, LINT, Formality, VSI, UPF, 0in, RTL Coding, IORING, SoC IP level integration, Design Partitioning

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes