Usb, Pcie, Test Plans, Verification environments, Regression management, SoC ASIC Verification, Waveform tools, Uvm, systemverilog, Coverage-driven verification, RTL design concepts, Axi, Test benches, APB, AHB

Perl, Verilog, Python, SV, Cadence or equivalent simulation tools, SV scripting languages

Debugging Tools, Perl, Python, Tcl, Uvm, systemverilog, LPDDR4, Axi, DDR verification, DDR protocols, DDR5, DDR4, AHB, LPDDR5

Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification

C, Spi, Shell, Verilog, I2c, System Verilog, Python, Uart, Can, Flexray, Perl, Ethernet, Cadence Tools, Xcelium, Uvm, UPF, GLS, safety simulator, VHDL, vManager, Formal applications, AMs, Axi, PSI5, APB, PAGLS, CPF, AHB

C, Verilog, Uvm

Performance Analysis, Linux drivers, workload characterization, systemverilog, CPU GPU benchmark characterization, performance analysis tools, SOC design verification, runtime, mobile SOC performance model development

arm architecture , Usb, DDR, Pcie, Perl, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, Arm system IP, SoC Verification