arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

C, Shell, Perl, Verilog, System Verilog, Python, Cadence Tools, Xcelium, Uvm, safety simulator, VHDL, vManager, Formal applications

DDR, Shell, Pcie, Perl, Python, JESD204B, Uvm, UPF, GLS, systemverilog, MIPI, Dft, USB3

Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, assertions coding

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB