Routing, Sta, ECO Implementation, EM, Ir, floorplanning, Signoff Checks, Physical Design, Si, Timing Closure, Placement Optimization, DRC LVS and Physical Verification, power analysis

Tcl Scripting, place route flows, LVS, sign-off methodologies, floorplanning, wire planning, DFT methods, Synthesis, physical design verification, Timing Closure, DRC, custom clock trees, Clock Tree Synthesis, Tessent flow