simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Sed, Jtag, Awk, Tcl, MBIST, gate-level simulation, Spyglass-DFT, Dft, Tessent, ATPG, Scan, LBIST

Sed, Jtag, Awk, Tcl, DFT features, debug skills, MBIST, gate-level simulation, Spyglass-DFT, test cost reduction analysis, ATPG, scan-stitching, Scan, scripting skills, LBIST, Tessent flow, post silicon support

Sed, Jtag, Awk, Tcl, LBIST, Dft, Tessent, ATPG, Scan, MBIST, gate-level simulation, Spyglass-DFT

Dft, Design For Testability, Scan Insertion, Scan Compression, DFT Compiler

boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis

boundary scan , Perl, Scripting Languages, Python, Tcl, scan compression, JTAG IEEE 1149.1, Scan Insertion, memory BIST, DFT methodologies, DFT EDA tools, test pattern generation, ATPG, silicon bring-up, post-silicon debug, Cadence Modus Genus