Tcl Scripting, Vivado Quartus or Libero Tools, RTL Design using Verilog VHDL, Hardware Debugging and Board Bring-up, FPGA Design Flow Synthesis Implementation P R Timing Closure, High-Speed Protocols PCIe Ethernet DDR Transceivers, FPGA Design and Validation, CDC Clock Domain Crossing Analysis, Simulation using Questasim, FPGA Integration Experience, Experience using Oscilloscopes and Logic Analyzers, Static Timing Analysis STA

Tcl Scripting, Verilog, Rtl Design, FPGA hardware platforms, VHDL, FPGA development, Questasim

Verilog, perl, python, Linux, Tcl, Vivado