Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA

Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, full verification life cycle, vector processing units, industry-standard simulators, AI ML Accelerators, systemverilog, hierarchical memory subsystems, revision control systems, Specman E, constrained-random verification environments, Verification, IP subsystem SoCs, packet processing, congestion control, regression systems, Debug

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

analog circuits , Fpga, Logic Design, Verilog, Micro-architecture, Synthesis, Uvm, Timing Constraints, Regression frameworks, Power product design, System-Verilog, Functional Verification, RTL Coding, Sta, Synthesis scripts, ATPG generation, Scan Insertion, formal verification, ABV, Timing Analysis, Digital Verification