Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Vcs, Shell, Perl, Python, Verdi, Assertions SVA, Verification planning, RISC-V, Regression and debug, UVM testbenches, Uvm, systemverilog, Test-plan development, Functional and code coverage, DDR verification, Questa

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi