Verilog, Python, VHDL, SV, HDLs, Formal Functional Verification, IBM Formal verification tools, Processor core u-arch

Usb, Pcie, Perl, Verilog, Shell scripting, Python, systemverilog, Axi, VHDL, Formal Verification Flow, APB, Cadence JasperGold, AHB

Python, Low Power Formal Methodology, Jasper VC Formal, formal verification, Formal Tools, Property-based FV, SVA, Questa Formal

Shell, Python, Perl, complexity reduction techniques, formal verification technologies, high quality testplans, formal testbenches

Tcl, Python, Perl, JasperGold, VC Formal, Questa Formal, formal verification methodologies

Tcl, Perl, JasperGold, digital design concepts, Questa, VC Formal, systemverilog, debugging complex design bugs, convergence techniques, formal coverage metrics, RTL coding in Verilog, Formal OneSpin, formal verification, formal property specification

Cadence JasperGold, Synopsys VC Formal, SVA, Digital Design, systemverilog

Python., Verification methodologies, formal verification tools, Uvm, systemverilog