Verilog, VHDL, formal verification, Chisel, JasperGold, VC Formal, Object-oriented Programming, systemverilog, Formal Abstraction Techniques

Perl, Verilog, Python, Tcl, SystemVerilog Assertions SVA, VHDL, Synopsys VC Formal, Cadence JasperGold, Property Specification Language PSL, systemverilog

C, Perl, Python, Tcl, Formal Verification methods, Formal verification techniques

Shell, Perl, Verilog, Automation Scripting, Python, Tcl, SVA, Protocol verification, Formal verification methodologies, systemverilog, RTL analysis, Temporal logic

formal verification, digital design concepts, debugging complex design bugs, Questa, convergence techniques, JasperGold, Formal OneSpin, VC Formal, formal coverage metrics, RTL coding in Verilog

Shell, Perl, Python, formal property verification, complexity reduction techniques, formal verification technologies, formal testbenches, testplans