control logic , Processor microarchitecture, CPU datapath expertise, Physical design implementation, ALUs, Execution units, Block-level tape-outs, FPUs, RTL to GDS implementation, Data-paths, High-speed digital logic

routing, congestion analysis, IR drop, primetime, floorplanning, physical ECO implementation, physical optimization, Cadence Innovus, LVS, Power Planning, Physical Verification, antenna checks, Calibre, Physical Design, StarRC, ERC, Timing Closure, DRC, Placement, sign-off, RTL-to-GDSII, Synopsys ICC2

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

Scripting, Unix, Clp, Perl, Linux, Tcl, floorplanning, PDN knowledge, LEC, PNR implementation, Optimization, STA flows, Placement

Perl, Tcl, Skill, EDA Tools, Cadence Virtuoso

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Shell, Perl, Python, Tcl, Calibre, ERC, pegasus, DRC, LVS, Antenna, ICV

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

Vulnerability Management, Bash, Python, AI tools, compliance-supporting security controls, Security Monitoring, security tooling administration, security automation playbooks

Tcl Scripting, Python, Synopsys DFT flow, Tool installation configuration, Dft, PrimePower, Virtuoso SI2 scripting, virtuoso, LEC, Voltus RedHawk, Power and signoff flow automation