Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

Django, PostGreSQL, Gcp, Python, dbt

ATPG - TestKompress, Simulation - VCS, MBIST - Mentor ETVerify, Shell, Perl

Yocto, Debuggers, C, Cmake, Device Drivers, Android, Docker, shell scripting, Linux, Qnx, Python, logic analyzers, Oscilloscopes, make, CI CD, Hypervisors, Test-Driven Development, qemu

Kibana, Github, Nlb, Maven, PostgreSQL, Prometheus, Kafka, Grafana, Shell, Docker, Terraform, Sonarqube, Oracle, Python, AWS, Elk Stack, Redis, Jenkins, Git, Gradle, Ansible, Apache Kafka, MongoDB, Helm, Kubernetes, Terragrunt, GitHub Actions, F5 Load Balancers, Apache HTTPD, ALB

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff

Python Scripting, Routing, Perl, Tcl, Flow Development Automation, Full-chip Physical Design, RTL to GDSII Flow, Signoff, CTS, Advanced Node Experience, floorplanning, STA and Physical Verification

redhawk , Scripting Languages, Python, Perl, Tcl, power analysis, primetime, PrimeClouser, Tempus, Cadence Innovus, manufacturing sign-off, DFT insertion, Voltus, ASIC SoC physical design, Calibre, EDA Tools, low-power design, EM IR analysis, advanced nodes, multi-clock domain handling, Timing Analysis, Physical Verification, reliability checks, Signal Integrity