System Verilog, chip design flow, constrained-random verification environments, design verification methodologies, hardware verification languages, Specman, ASIC standard interfaces, verification techniques, performance verification of ASICs, memory system architecture

Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

coverage closure, Gate level simulations, real number modeling, System Verilog UVM, Vplan regression

Ovm, Test and coverage plan, Assertion checkers, System Verilog HVL, VMM Test Harness, Uvm, Validation plan, Coverage and scenario creation, Verification environment

System Verilog, Axi, dv methodologies and tools, ACE-Lite, Uvm, LPDDR5 protocols, Digital design concepts, Bus protocols like AHB, Ace, Debug

code coverage , Scoreboards, Functional coverage, Assertions, RTL verification using Verilog and SystemVerilog, Constrained-random verification environments, Verification closure methodologies, Testbenches, Regression management, Coverage-driven verification techniques, Developing verification plans, Digital Verification