Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog

System Verilog, chip design flow, Specman, performance verification of ASICs, ASIC standard interfaces, constrained-random verification environments, verification techniques, design verification methodologies, hardware verification languages, memory system architecture

System Verilog, Finesim, HSIM, Test Bench development, XA hspice, Uvm

arm architecture , Branch-Predictor Frontend Load-Store verification, cache coherency concepts, stimulus generation using RIS tools, ARM v9 architecture, CPU microarchitecture verification

Fpga, Asa, Pcie, Technical Leadership, System Verilog, Uvm, Maxim GMSL protocol standard, USB 3, VIP development, FuSa verification, Effort and schedule estimation tracking, MIPI, AMS Verification, Grounds up verification environment development, TI FPD

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm