Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC

python, Perl, System Verilog, DDR-IO verification, LPDDR JDEC specifications, Uvm, coverage driven verification methodology, LPDDR5

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Tcl, Verilog, C, Python, Perl, Shell, UVM methodology, systemverilog, EDA Tools

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

Verilog, System Verilog, FPGA tools, Synthesis, formal property verification, timing constraints development, RTL Coding, assertions, uArch, CDC checks