Logic Design, System Verilog, Armv7-A processor architecture, Micro-Architecture Design, Axi, Synthesis, Cortex A9, VHDL, APB, Equivalence checking, RTL Coding, Cortex A7, AHB, Lint and CDC, Digital Design

System Verilog, Coverage models, DV methodology, Testbench design, Uvm

static timing analysis, Verilog, Debugging, Integration, Synthesis, multi-clock domain architectures, digital design fundamentals, power optimization techniques, low-power design methodologies, micro-architecture development, Physical Design, systemverilog, Dft, Axi, APB, Timing Closure, RTL Coding, Verification, AHB

arm architecture , C, Usb, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

Technical Documentation, RTL design and verification, analog circuit design and integration, circuit simulation tools, mixed-signal environments, validation and debugging, Spice, Cadence

Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures

arm architecture , C, Ethernet, Pcie, Usb, DDR, assertion-based formal verification tools, Uvm, SoC DV execution, TLMs in SystemC, HBM, hardware emulation support