Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Assertion checkers, Uvm, MIPI, Validation plan, System Verilog HVL, Coverage and scenario creation, VMM Test Harness

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog