Tcp Ip, Pcie, Perl, Shell scripting, Ethernet, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies, networking IP solutions, Verilog RTL design, Design for Test methodologies, DMAs, NVMe based Storage IP

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, Timing Closure, 5G LTE, Altera Agilex

Shell scripting, Tcp Ip, Ethernet, Pcie, Perl, DMAs, Design for Test methodologies, NVMe based Storage IP, Verilog RTL design, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies

Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools

Digital Logic Design, Micro-architecture design, RTL quality checks, SOC Integration, Rtl Design

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

memory controllers , Verilog, Flash, Ddr3, physically aware design flows, LPDDR, Security, UCIe, systemverilog, multi-clock domain architectures, Ram, AHB, clocking system modes, Synthesis, Axi, D2D protocols, Rom, Bunch-of-wires, CHI, Memory, Sta, Rtl Design, power optimization techniques, Timing Closure, low-power design techniques, power management, Debug