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RTL design Engineer with UPF ( Unified Power Format )

AMD Ventures
Hyderabad, India

Skills:

Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

Early Applicant

RTL design Engineer with UPF ( Unified Power Format )

AMD Maquinaria
Hyderabad, India

Skills:

Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

Early Applicant

Staff DRAM RTL design engineer

Micron Technology
Hyderabad, India

Skills:

LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

Early Applicant

Senior Staff, RTL Design Engineer

Renesas Electronics
Hyderabad, India

Skills:

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Early Applicant

RTL Design Engineer

jobworld india private limited
Hyderabad, India

Skills:

RDC, RTL coding expertise in Verilog, SpyGlass Lint, micro-architecture development, systemverilog, FSM design, Pipelining techniques, ASIC SoC design flow, Datapath architecture, cdc, Clock and Reset domain crossings

Early Applicant
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