Perl, Tcl, Skill, EDA Tools, Cadence Virtuoso

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

Tcl Scripting, Python, Synopsys DFT flow, Tool installation configuration, Dft, PrimePower, Virtuoso SI2 scripting, virtuoso, LEC, Voltus RedHawk, Power and signoff flow automation

DFT verification, IEEE1149, CTL generation, MBIST, Scan, ASIC SoC designs, DFT validation, 1500, 1687, DFT EDA tools, Dft, timing generating test cases, Analog IPs, HSIOs, debugging GLS

boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST

synopsys tools , MBIST controller, MBIST implementations, Repair Techniques, SoC level simulations, ICL Extraction, DRC for all modes, Compression Techniques, retarget from SoC level for SCAN, DFT architecture, Tessent, ATPG, JTAG Implementations, SCAN implementation, pdl, Memory grouping, Scan DRC fixes, clocking architecture