Verilog RTL coding, Formal verification tools

Verilog, System Verilog, RTL Coding, Full Chip Integration, System Verilog assertions, scripting in Perl

Pcie, Verilog, Ethernet, Debugging, Scripting, Python, Tcl, digital design fundamentals, UCIe, systemverilog, high-speed IO protocols, Problem-solving, Rtl Design, CXL, micro-architecture, low-power design techniques

Pcie, Verilog, System Verilog, RTL Coding, CXL, FPGAs

Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST

Verilog, System Verilog, scripting in Perl, System Verilog assertions, RTL Coding

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

synopsys primetime , Pvs, Perl, Python, Tcl, Mentor Calibre, Cadence Pegasus, PowerSI, ICC2, clock gating, Cadence Innovus, Synopsys Fusion Compiler, UPF, Synopsys IC Validator, Ansys RedHawk, CPF

Coding, Usb, Verilog, Ethernet, Pcie, Sata, Rtl Design, RTL, ASIC Design, Principal