Job Title:

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor's or Master's degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You're adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines.

Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you're known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You're seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals.

What You'll Be Doing:

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.
Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.
Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.
Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

The Impact You Will Have:

Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies.
Contribute to the successful execution of complex, global projects that set new standards in chip design and verification.
Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions.
Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation.
Drive improvements in design quality, efficiency, and scalability through process optimization and automation.
Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends.

What You'll Need:

Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or related field.
4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.
Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.
Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.
Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).
Exposure to quality processes in IP design and verification is an advantage.
Prior experience as a technical lead or mentor is highly desirable.

Who You Are:

Innovative thinker with a solutions-oriented mindset and a passion for technology.
Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.
Natural leader with mentoring abilities, fostering inclusion and diversity within the team.
Detail-oriented professional with strong analytical and problem-solving skills.
Self-motivated, adaptable, and eager to drive technical excellence and process improvements.
Committed to continuous learning and staying ahead of industry trends.

The Team You'll Be A Part Of:

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

ASIC Engineer Staff

Staff Engineer, ASIC Development Engineering (IP Verification )

ASIC RTL Design Engineer (Sr. Lead / Staff)

ASIC Digital Design Verification, Staff Engineer

Staff ASIC-DV Engineer

IP Design Technical Lead/ Staff ASIC RTL Design Engineer