ASIC Digital Design Verification, Staff Engineer

What You'll Be Doing:

• Developing and reviewing verification plans for SERDES/PHY/Controller IPs.
• Creating and maintaining verification environments, with a preference for UVM.
• Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure.
• Delivering high-quality RTL and simulation models to customers.
• Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems.
• Supporting customers with IP integration, silicon bring-up, and debugging issues.
• Demonstrating Testchip+FPGA system demos to customers and at conferences.

The Impact You Will Have:

• Ensuring the compliance and functionality of our interface IPs with industry protocols.
• Enhancing the quality and reliability of our silicon solutions for customers.
• Facilitating smooth customer adoption and integration of our IPs.
• Contributing to successful silicon bring-up and debugging efforts.
• Showcasing our technological advancements at industry events.
• Driving innovation and excellence in digital design and verification processes.

What You'll Need:

• Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B).
• Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Experience with SERDES/PHY/Controller IP specification and compliance validation.
• Strong background in developing and reviewing verification plans and environments.
• Ability to deliver high-quality RTL and simulation models to customers.