Tcl Scripting, Python, System Verilog, HW–SW interaction, SoC TB architecture, test-plan creation, UPF-based methodologies, debug skills, UVM methodology, RTL integration, DV sign-off flows, gate-level simulation, power-aware verification

Pcie, Ovm, Scripting, System Verilog, Ethernet, Uvm, HBM2, HBM3, Memory protocols, GDDRx, SVA, AHB, LPDDR4, AMBA standards, APB, High speed SerDes, Axi

Ovm, SOC design, Design Verification

System Verilog, Ovm, Debug, Validation Verification, Uvm, verification architecture, Emulation, validation test suites, coverage closure, test plan execution, Silicon Design, constrained random verification methodologies

System Verilog, SoC Verification, Rtl Design, Design Verification, Uvm, Asic verification

Vcs, Perl, Python, Tcl, Debugging methodologies, Verdi, Assertions SVA, Xcelium, Uvm, ASIC SoC Verification Flows, systemverilog, Coverage-driven verification, spyglass, Simulation and regression flows, Jenkins Regression Automation Tools, DVE, Questa, Functional Verification

ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols