Scala, Python, DevOps practices, EDA Tools, build systems, Chisel, CI CD

Python, Uvm, Emulation, Palladium, AMBA, Veloce

Logic Design, Rtl Design, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Static-timing closure, Custom SoC ASIC products, Gate-level simulations, Block-level function verification, formal verification

DDR, Pcie, Ovm, Ethernet, System Verilog, UFS, CHI, VMM, ARM Based SoC Verification, Uvm

Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis