Linux Scripting, Python, Tcl, Regression Testing, OCV, flow validation regression testing, setup hold analysis, STA infrastructure automation, SI-aware timing analysis, MMMC setup, voltage-aware STA methodologies, timing signoff methodologies, POCV implementation, STA flow and signoff methodology, AOCV, QoR correlations

Scripting, Automation Tools, Verilog, Python, Perl, Automotive qualification, Uvm, Analog Circuit Design, systemverilog, DACs, ADC, Cadence, Formal verification methodologies, Op-Amps, ISO26262, Comparators

Python Scripting, Layout implementation, SRAM compiler development, Transistor-level circuit design, Debug of SRAM macros, Silicon testing, Cadence schematic and layout capture tools, SRAM design, Physical and logical verification

clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes