DDR Timing, SDRAM functionality, ASIC design flow, ESD concepts, ODT, analog mixed signal design methodologies, JEDEC DDR interface requirements, layout methodologies, CMOS Circuit Design

bandgap references , power converters , Design extraction and simulation flows, Analog layouts, Source-Sink LDOs, Voltage Regulators, High speed level shifters, Current Sense SAR ADCs, FET layouts, Analog Circuit Design, Temperature Sensor, Power Management ICs, Switch Cap circuits, Ultra-low power Oscillators, Comparators, Op-Amps, Noise isolation techniques, Analog Buffers, Charge Pumps

Ultra high speed serial IO link HSS interface, Layout extraction methodology, 7nm 14nm FinFET technology, Post layout simulation, 32G 50G 112G IO link interfaces, Analog Circuit Design, Full custom analog circuits, CAD tool flow for 7nm 14nm process

bandgap references , Usb, Pi, Ddr3, Dll, Sata, Pcie, DFE, Bias generator, High speed Memory interfaces, Clktree, SerDes Interfaces, MIPI, Charge pump, HDMI, Analog mixed signal CMOS circuits, HBM2E SoC analog sub-block design, DDR5, Rx CDR, GDDR5, OPamps, LDO, LPDDR3, Tx PLL, Comparators

CMOS Circuit Design, Deep submicron process technology, Analog/mixed-signal circuitry basics, DDR/HBM memory interface design, ASIC design flow, JEDEC standards for DDR interfaces

DC-DC Design, Power Electronics, Pcb Layout, Circuit Simulation, Analog Design, Validation

Schematic design, Microsoft Office, SKM software, Electrical, ANSI, GIS data, CAD, Relay coordination, Power Generation, nesc, NCEC, NERC standards, Etap