Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Synthesis, Formal Equivalence, Extraction, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

redhawk , Scripting Languages, Python, Perl, Tcl, power analysis, primetime, PrimeClouser, Tempus, Cadence Innovus, manufacturing sign-off, DFT insertion, Voltus, ASIC SoC physical design, Calibre, EDA Tools, low-power design, EM IR analysis, advanced nodes, multi-clock domain handling, Timing Analysis, Physical Verification, reliability checks, Signal Integrity

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Python Scripting, Routing, Perl, Tcl, Flow Development Automation, Full-chip Physical Design, RTL to GDSII Flow, Signoff, CTS, Advanced Node Experience, floorplanning, STA and Physical Verification

Unix, Perl, Verilog, System Verilog, Python, Tcl, Synopsys Fusion Compiler, PPA tradeoffs, Power Planning, Physical Design, Timing Closure, Innovus, Timing Power EM IR PDV

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Physical Design, SDC STA, Python Script, PnR tools like ICC2 Innovus, Equivalence checking, Skill