redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

power optimization , static timing analysis, routing, Verilog, Synthesis, power distribution analysis, submicron process node technologies, power delivery methodologies, Power Estimation, reliability verification, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2

Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks

routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow