Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis

layout verification , very large scale integration (VLSI) design, system on a chip (SoC), System Verilog, clock voltage domain crossing design for testing DFT, ASIC Design, design rules, low power designs

hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation