Perl, Tcl, Full-custom memory layout development, EDA Tools, ERC, EMIR analysis, DRC, LVS, Cadence Virtuoso

Prometheus, Bash, Grafana, Jira, Jenkins, Git, Confluence, Bitbucket, Perl, Openshift, Python, Kubernetes, GitOps, OpenShift pipelines, DevOps methodology, Tracing service mesh

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, primetime, Block and subsystem-level physical design flows, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Cadence Innovus, Tempus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Scripting, Floor-Planning, AI tools, Cadence, RTL2GDS flow, Chip Finishing, flow automation, Physical Verification, Synthesis, Physical Design, Power Distribution, Metal Dummy Fill, Synopsys, Place And Route, Clock Tree Synthesis

Perl, Python, Tcl, Physical verification and ECO implementation, primetime, Floorplanning and physical architecture, Tempus, Cadence Innovus, Timing closure and SI debugging, CTS and clock distribution optimization, IR EM and power integrity analysis, Synopsys ICC2

Logic Design, Synopsys, MBIST OCC validation flows, IEEE 1687 IJTAG standards, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, Cadence, DFT for complex ASIC SoC designs, SSN design, Physical design flows, RTL design synthesis