Computer Architecture, C, Makefile, Hdl Programming, Digital Logic Design, Perl, Verilog, Ruby, Python, System Verilog, UNIX Software Environment, AI Tools, Logic Simulation, Functional Verification, Simulation and Debugging

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, System Verilog constraints structures and classes, Palladium, Verifying sophisticated blocks clusters and top level for ASIC, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

Foundry DRM, IC Validator, ASIC PV, ESD verification methodologies, Calibre ICV, pegasus, DRC, Physical Verification, LVS, Advanced nodes 4nm and below

Shell, Perl, Python, complexity reduction techniques, formal verification technologies, high quality testplans, formal testbenches, root-causing counter-examples

bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, IP subsystem SoCs, congestion control, systemverilog, constrained-random verification, packet processing, Verification, standard IP components