Work Expertise : 5 Years - 15 Years
Desired Profile :
- Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PV
- Expertise in physical verification with full signoff ownership
- Expertise in DRC, LVS and ESD verification methodologies
- Expertise in Calibre, ICV (IC Validator) or Pegasus
- Expertise in foundry DRM : able to read, interpret, and implement complex rule decks
- Expertise in advanced nodes 4nm and below
- Expertise in using AI agents to drive automation across verification flows and tapeout signoff
Job Specs :
- Own and execute full-chip DRC, LVS, ESD, and antenna signoff using Calibre, ICV, or Pegasus
- Develop, maintain, and optimize physical verification flows for advanced node SoC and 3D IC designs
- Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
- Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
- Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
- Drive tapeout readiness by coordinating signoff across block and top-level design teams
- Engage directly with foundry teams to resolve DRM ambiguities and waiver requests
- Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
