PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

, Tcl, Perl, Fc, Routing, Python, Scripting, Synthesis, LEC, EDA Tools, Calibre, floorplanning, EMIR, ICV, Tempus, Placement, ERC, DRC, Power Planning, Genus, power analysis, Dc, LVS, Pt, pegasus, Physical Verification, Innovus, ICC2, formal verification

PYTHON, PERL, Scripting Languages, Tcl, Scan-DRC tk methodology, Fusion compiler, PnR tools, low power methodologies, FV CLP, PD ownership, PDN STA, LEC low-power checks, ASIC designs, PDN STA closure, Innovus, CTS issues, Sign-off PV, HM level PV, debugging Congestion, Place and Route flow, Voltage Islands

Tcl, PYTHON, Shell, Physical Design, Multi-point CTS, FinFET Dual Patterning nodes, Custom-CTS, Flex-H, innovus tool, PD-flow EDA-tools scripts, STA constraints, PD metrics dashboard scripts