Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog

Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Python, Perl, Pcie, Uvm, JasperGold, LPDDR, VC Formal, CHI, Ace, GPUs, Verdi, Synopsys VCS, ARM CPU, Cadence Xcelium Simulator, DLA, HBM, Axi, Network on chip, AMBA protocols, ATB

System Verilog, Vcs, DRAM memory controllers, Questa, Uvm, Xcellium, AXI4 bus protocol, Riviera, Vivado

Scripting (Perl/Python/Shell), SystemVerilog/UVM, DDR/LPDDR Protocols, Functional and Code Coverage, RTL Design and Debugging, Assertion-Based Verification, IP verification

Linux, Perl, C++, System Verilog, Firmware, Ip, Digital Design

simvision , Hspice, Finseim, Xcellium, debugging complex Analog Digital Mixed-Signal circuits, scripting skills using perl, MS RVM model writing, AI-related tools, verilog a, SV PSL assertions, Analog and Mixed signal Verification, Analog mixed signal circuits, virtuoso, Verilog Models, Waveview, COSIM Mixed signal verification environment, SV UVM based Verification, SPICE testbenches, primesim