simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

boundary scan , Python Scripting, Jtag, Perl, Verilog, System Verilog, Tcl, DFT verification, silicon debug, TAP, MBIST, IEEE 1687, ATPG, Scan Compression, IEEE 1149.1, IJTAG

Scan Insertion, DFT methodology, Fault modeling, EDA Applications

logic bist , static timing analysis, UNIX, Jtag, Linux, Perl, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell

Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion

Gate level simulations, Synthesis, Timing Constraints, Logicbist insertion, ATPG, Digital RTL coding, Siemens, Cadence, Mentor, Synopsys, TetraMax

logic bist , static timing analysis, UNIX, Jtag, Perl, Linux, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan, c-shell

boundary scan , Tcl, Python, Perl, Scripting Languages, test pattern generation, silicon bring-up, scan compression, JTAG IEEE 1149.1, ATPG, DFT EDA tools, post-silicon debug, DFT methodologies, Cadence Modus Genus, memory BIST, Scan Insertion