Soc Architecture, Asic, systemverilog, CAD Tools, Rtl Design, SoC Integration

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles