Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

Pcie, Verilog, Networking Protocols, Static timing analysis, Timing closure methodologies, RDC analysis, RTL implementation, Synthesis, AMBA-AXI, Power methodology development, systemverilog

ASIC development cycle, ASIC design methodologies, develop solutions, cross-functional teams, Rtl Design, architecture, Verification

Verilog, System Verilog, FPGA tools, Synthesis, formal property verification, timing constraints development, RTL Coding, assertions, uArch, CDC checks

Git, Pcie, Perl, Verilog, Ethernet, Shell scripting, Static Timing Analysis, Python, System Verilog, Tcl, LINT, Sta, cdc, Dft, Synthesis, AXI-based interconnects, RDC, CXL

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools