Perl, Python, Tcl, formal verification, JasperGold, VC-Formal, systemverilog, SVA

HDLs (Verilog, SystemVerilog), Assertion-Based Verification (SVA), Debugging, Python, VHDL, formal verification, Verification Environments, Functional Verification, IBM Formal Verification Tools, Testbenches

Scripting, Cpu, Gpu, Formal Verification Tools, formal verification, Temporal Logic Assertions, Verification Fundamentals

NOC (Network on Chip), HLS (High-Level Synthesis), power optimization , CDC (Clock Domain Crossing), Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, Formal Verification Methodology, Shell-scripting, Memory and Peripheral Subsystems, Data path development, Synthesis, Timing Closure, Implementation Power methodology development, Micro-architecture and RTL development, Power Analysis and Optimization

Networking, Ovm, Test Methodologies, Pcie, Automation Frameworks, Ethernet, Emulation platforms, Uvm, Simulation Tools, Axi, AMBA, Design Verification, Verification infrastructure

PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

Verilog, SoC Verification, formal verification techniques and tools, model checking, equivalence checking, VHDL

Data Flow Graphs (DFG), Binary Decision Diagrams (BDD), Verilog, System Verilog, model checking, abstraction modeling, formal verification tools, convergence strategies, equivalence checking, simulation techniques

Python, UPF, formal tools, Questa Formal, isolation, power clock gating, SVA, Retention, formal verification, property-based FV, Jasper VC Formal, CPF

Verilog, Chisel, VHDL, JasperGold, formal verification, VC Formal, systemverilog, Formal Abstraction Techniques, Object-oriented Programming