Routing, power analysis, Physical Verification, Physical Design, floorplanning, Timing Closure, Placement, DRC, LVS, Signal Integrity, Rtl Design

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

hardware engineering , Deep sub-micron technology, ASIC design flows, Physical design methodologies, Circuit Design, device physics, Floorplan, Netlist2GDS

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies

C, Perl, Tcl, Physical Verification, Clock Planning, Placement and Routing, floorplanning, Timing Closure, Physical Design Implementation

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology