
Search by job, company or skills
Showing 9 jobs
Skills:
C, Routing, Perl, Tcl, Clock Planning, primetime, floorplanning, ICC2, LEC, Calibre, Innovus, Physical Verification, Placement, Timing Closure, Physical Design Implementation, EDA Tools
Skills:
Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop
Skills:
redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques
Skills:
Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route
Skills:
Perl scripting, PrimeTime-SI, primetime, Antenna Checks, LVS, Substrate Bias, IR Drop Analysis, low power design, Physical Verification, Physical Design, Timing Closure, Synopsys Physical Design tools, Power Gating, Floor Planning, DRC, Voltage Islands
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis
Skills:
PERL, Python, Tcl, Sta, CTS, Timing Convergence, RTL2GDSII flow, ICC2, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure
Skills:
clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, Power Mesh, PNR Floor Plan, Timing Signoff
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
