ShotPlus™ UG, Underground drill and blast design, Deswik underground mine planning software, Electronic blasting technologies, Mine Planning, WebGen™, Stope design and evaluation

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

Perl scripting, PrimeTime-SI, primetime, Antenna Checks, LVS, Substrate Bias, IR Drop Analysis, low power design, Physical Verification, Physical Design, Timing Closure, Synopsys Physical Design tools, Power Gating, Floor Planning, DRC, Voltage Islands

Generation of detailed parasitic information, Signoff Static Timing Analysis, Static and Dynamic rail analysis, Block level floor planning, LVS, Signal integrity analysis, Physical Verification, Design for yield techniques, Timing driven placement and routing, DRC, Place And Route, Timing-optimization tasks, Power routing

Routing, Automation, LPDDR5, Verification processes, HBM3, DDR5, Design validation, Tape-out revisions, Floor-planning, Modeling and simulation, Parasitic modeling, LPDDR6, Memory Logic Analog circuits, Placement

Tcl, PERL, Cadence, Floor Planning, SI Aware Routing, Synopsys, Voltage Islands, Timing Analysis Closure, ECO Tasks, Physical Verification, Timing Optimization, Substrate-bias Techniques, Asic Physical Design, Power Gating, Physical Design, Timing Closure on High Speed Interfaces, low power design, IR Drop Analysis, Antenna Checks, Signal Integrity Closure

layout planning, nanometer CMOS, compiler usage, physical implementation, schematic capture, margin verification, Memory Architecture, variation-aware design techniques, characterization, Circuit Design, Simulation

Coding, C, coverage closure, low power design verification techniques, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, x86 ISA, systemverilog

Design Verification, Uvm, Verification Planning, systemverilog