Vcs, Verilog, Gdb, ASIC design flow, Rtl Design, floor-planning, Eco, Timing Analysis, Debussy, bring-up lab debug

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

static timing analysis, Synthesis, Front End SoC quality efficiency guardrails, SoC integration, low-power design architecture verification, 6G Radio Solutions, clock domain crossing, Soft Radio SOCs, Rtl Design, 5G, Optimization Techniques, formal equivalence checking, low-power design

low power design, LINT, cdc, Charging voltage regulation, Interconnect fabrics, Clock domain crossing, Battery management, Familiarity with Cadence Synopsis design tools, Synthesis, Verilog Coding, RDC, Serial interfaces, Register file design, Power intent specification and validation methodology, RTL Coding, Microarchitecture Module design and simulation, Scan and self-test, State machine architecture, Knowledge of TFM Tools Flows and Methodologies, ARM based Subsystems SOCs, Verification including System Verilog knowledge, Synthesis Linting STA, Simulation, Automation scripting and design flows, Digital design implementation and integration

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

Synthesis, RTL code in Verilog, SoC integration, Timing Closure, RTL logic design, micro-architecture specifications, Verification, timing optimization, assertions coverage analysis

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification